As a test carrier on which a semiconductor chip in a bare chip state is temporarily mounted, there is known one which clamps the semiconductor chip between a lid member and a base member in an atmosphere which is reduced in pressure compared with the outside air (for example, see PLT 1).
The lid member of this test carrier is formed with interconnect patterns which correspond to electrodes of the semiconductor chip. The semiconductor chip is connected through these interconnect patterns to an outside test apparatus.